Make ChiselEnum take parameters (to make the width adjust as necessary)

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: request

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

**What is the current behavior?**

If I build a ChiselEnum with lots of values, the width of the signal is adjusted accordingly.
But sometimes I may know that some values will never be used in given configurations, yet the width will always be the maximum necessary to accomodate all the values.

For example: https://scastie.scala-lang.org/3uueK6ybS9S3wjFrRJ6OSA

**What is the expected behavior?**

If setting the above `true` to `false` the code would compile and the width of the wires would only be 1 bit to accomodate the 2 enums
**Please tell us about your environment:**
- version: 3.5.1

**What is the use case for changing the behavior?**

Be more explicit about optimized hardware in terms of narrower wires/ less impossible coverage