chipsalliance / chipsalliance/chisel
Prefix Graph(Tree) Config API
- Dominant language
- Scala
- Stars
- 4.8k
- Forks
- 658
- Avg merge
- 18h 59m
- Merged PRs (30d)
- 14
Description
It's possible to add a prefix graph API to fine granularly control circuit PPA and optimize for post synthesizing from Chisel:
This can benefit Add/Sub LeftOr/RightOr and other APIs
**Type of issue**: feature request
**Impact**: API addition (no impact on existing code)
**Development Phase**: proposal
**Other information**
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
**What is the current behavior?**
expose + - * / as primitive, throw optimization effort to synthesis tools.
**What is the expected behavior?**
An prefix graph API to let user fine tune the adder(or other circuit) that is used by Chisel.
**Please tell us about your environment:**
Chisel3.6-SNAPSHOT
**What is the use case for changing the behavior?**
fine tune to combinational circuit
Contributor guide
Research direction
Start by reviewing the existing Add/Sub LeftOr/RightOr APIs and how Chisel currently exposes primitive +, -, *, and / operations. Define the proposed prefix graph API and its user-facing configuration scope, then verify that it enables circuit fine-tuning for post-synthesis optimization without affecting existing code.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 20/100