Weird verilog emit for cascade muxes

**Type of issue**: bug report

**Impact**: unknown

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
To generate cascade muxes like this:
```
out := MuxLookup(sel, 0.U(width.W),
(0 until num).map(_.U) zip in
)
```
val out is Reg type.
Whole file:
https://github.com/lxu28973/chisel-tmp/blob/e696a575cae2e41a508eaf4e3f55b725044eb447/src/main/scala/gcd/MUX.scala#L49-L51

**What is the current behavior?**
The emitted verilog describes select logic using "if else" in the always block and "z = s ? a : b" format.
Although the function is right, the verilog code style is weird.
I don't know whether it will affect subsequent optimization in synthesis tool.

The emitted verilog:
```
module MUX16(
input clock,
input reset,
input io_in_0,
input io_in_1,
input io_in_2,
input io_in_3,
input io_in_4,
input io_in_5,
input io_in_6,
input io_in_7,
input io_in_8,
input io_in_9,
input io_in_10,
input io_in_11,
input io_in_12,
input io_in_13,
input io_in_14,
input io_in_15,
input [3:0] io_sel,
output io_out
);
reg out; // @[MUX.scala 41:32]
wire _out_T_15 = io_sel == 4'he ? io_in_14 : io_in_15; // @[MUX.scala 53:359]
wire _out_T_16 = io_sel == 4'hd ? io_in_13 : _out_T_15; // @[MUX.scala 53:333]
wire _out_T_17 = io_sel == 4'hc ? io_in_12 : _out_T_16; // @[MUX.scala 53:307]
wire _out_T_18 = io_sel == 4'hb ? io_in_11 : _out_T_17; // @[MUX.scala 53:281]
wire _out_T_19 = io_sel == 4'ha ? io_in_10 : _out_T_18; // @[MUX.scala 53:255]
wire _out_T_20 = io_sel == 4'h9 ? io_in_9 : _out_T_19; // @[MUX.scala 53:231]
wire _out_T_21 = io_sel == 4'h8 ? io_in_8 : _out_T_20; // @[MUX.scala 53:207]
wire _out_T_22 = io_sel == 4'h7 ? io_in_7 : _out_T_21; // @[MUX.scala 53:183]
wire _out_T_23 = io_sel == 4'h6 ? io_in_6 : _out_T_22; // @[MUX.scala 53:159]
wire _out_T_24 = io_sel == 4'h5 ? io_in_5 : _out_T_23; // @[MUX.scala 53:135]
wire _out_T_25 = io_sel == 4'h4 ? io_in_4 : _out_T_24; // @[MUX.scala 53:111]
wire _out_T_26 = io_sel == 4'h3 ? io_in_3 : _out_T_25; // @[MUX.scala 53:87]
assign io_out = out; // @[MUX.scala 56:10]
always @(posedge clock) begin
if (reset) begin // @[MUX.scala 41:32]
out <= 1'h0; // @[MUX.scala 41:32]
end else if (io_sel == 4'h0) begin // @[MUX.scala 53:15]
out <= io_in_0;
end else if (io_sel == 4'h1) begin // @[MUX.scala 53:39]
out <= io_in_1;
end else if (io_sel == 4'h2) begin // @[MUX.scala 53:63]
out <= io_in_2;
end else begin
out <= _out_T_26;
end
end
endmodule
```
**What is the expected behavior?**
The emitted verilog describes select logic using "if else" in the always block **or** "z = s ? a : b" format, but not both. These two styles should not be mixed.

**Please tell us about your environment:**
- version: 3.5.1