chipsalliance / chipsalliance/chisel
Propose a regression CI infra for bumping Chisel versions.
- Dominant language
- Scala
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Description
Although most of new features have their own unittest, they still not successfully cover some corner cases.
I'm proposing a new CI infra to test some big projects(RocketChip/Chipyard/Xiangshan) with latest Chisel/FIRRTL. new PRs won't be blocked by this giant test. But it will help us to spot most of compatibility bugs before doing releasing.
I'm maintaining a [sequencer/playground](github.com/sequencer/playground) to absorb RocketChip and Chipyard repositories to make them depends on master Chisel and FIRRTL, I think this can be a good start point.
**Type of issue**: feature request
**Impact**: no functional change
**Development Phase**: proposal
**Please tell us about your environment:**
- version: master
- OS: Linux
**What is the use case for changing the behavior?**
Help releasing quality.
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Assessment
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