FIRRTL BlackBox and user-defined cache procedure.

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: proposal

**Please tell us about your environment:**
x.5-SNAPSHOT
**What is the use case for changing the behavior?**
Recently I have been thinking about the question: How to cache during multiple elaborations?

IMHO, I think a FIRRTL blackbox might help by directly linking user-defined "key" to generated FIRRTL as "value":
A key should be a serializable parameter, and user should make sure the reproducibility by them self, a FIRRTL module, as well as inner module and corresponding annotation will automatically be serialized by FIRRTL compiler. In side FIRRTL, we can use namespace to get rid of the name conflicting problem.
So I'm proposing a new API to Chisel and FIRRTL:
1. FIRRTL blackbox which works as what Verilog does, but it is a FIRRTL circuit.
2. the `CacheAnnotaion(key, circuit)` and API to end users to leave the cacheablity and reproducibility problem to end user.
3. A `CacheTransfrom` which insert the elaborated FIRRTL and annotation to main FIRRTL.

The proposal names no files, tests, or entry points. Start by locating the Chisel and FIRRTL compiler APIs for black boxes, annotations, and transforms, then define the cache key and circuit flow before determining what tests would demonstrate a completed design.

Written by the indexing model from the issue text.