Subfield assignment error message unhelpful

**Type of issue**: other enhancement

**Impact**: no functional change

**Development Phase**: request

**Other information**

**What is the current behavior?**

Currently, attempting to assign a subfield like so:
```scala
cmdq_wrdata(127,0) := rxIO.rx_wrc_rd_data
```

results in a pretty confusing exception `chisel3.internal.ChiselException: Cannot reassign to read-only UInt<128>`.

**What is the expected behavior?**

Something that explains that subfield assignment isn't allowed and suggests using vectors bundles (even though I'm of the belief Chisel should support something so natural to hardware engineers as bit assignment).

**Please tell us about your environment:**
version: 3.4.1
**What is the use case for changing the behavior?**
Give better guidance on subfield assignment. A majority of people starting from SystemVerilog who look at https://github.com/freechipsproject/chisel-cheatsheet are going to try extracting the bitfield and then assigning to that bitfield. While I believe this should be legal in Chisel, if it's not going to be, it should at least be clear to the user as to what's going on.

Since https://github.com/chipsalliance/chisel3/issues/878 is closed and fwiw: I'm planning to use blackboxes / inline verilog to get around the issue of not being able to directly do subfield assignment.