chipsalliance / chipsalliance/chisel
Request DataMirror being able to reflect more things
- Dominant language
- Scala
- Stars
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- Avg merge
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Description
**Type of issue**: feature request
**Impact**: API addition (no impact on existing code)
**Development Phase**: request
**What is the use case for changing the behavior?**
DataMirror currently have APIs below:
```scala
def widthOf(target: Data): Width
def specifiedDirectionOf(target: Data): SpecifiedDirection
def directionOf(target: Data): ActualDirection
def checkTypeEquivalence(x: Data, y: Data): Boolean
def modulePorts(target: BaseModule): Seq[(String, Data)]
def fullModulePorts(target: BaseModule): Seq[(String, Data)]
```
It can check:
`direction`, `width`, `typeEquivalence` from `Data`,
`Ports` from `BaseModule`
However chisel can provide more reflections from `Builder`, for example:
1. Hardware Type(from `Data.topBindingOpt`)
2. `instance`, `reg`, `mem` in a specific module.(like what `chisel3.aop.Select` did, but reflect during runtime.)
This can help library writer to provide more magic to users.
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