Feature Request: create a standard library for bus interfaces

If chisel came with standard bundles for popular bus interfaces (amba, tilelink and wishbone), then that would allow community members to write components using these standardized bundles and thus allow for much better interoperability.
I specifically am **not** suggesting that we move any actual implementation of bus components, nor any diplomacy support into chisel. Just the bundle definitions and in a second step - maybe - some generic monitors/checkers for the bus protocols.

A good starting point would be the bundles already defined in rocket chip for [amba](https://github.com/chipsalliance/rocket-chip/tree/master/src/main/scala/amba) and [tilelink](https://github.com/chipsalliance/rocket-chip/tree/master/src/main/scala/tilelink).

I am curious to hear everyone's thoughts on this.