chipsalliance / chipsalliance/chisel

Cannot use `--target-dir` in `runMain`

Open
#2,042 1 comment 0 reactions 0 assignees View on GitHub
Dominant language
Scala
Stars
4.8k
Forks
658
Avg merge
18h 59m
Merged PRs (30d)
14

Description

**Type of issue**: bug report | documentation

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

- Generate a chisel project via chisel-template
- Add these lines to GCD.scala
```scala
object VerilogGCD extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new GCD())
}
```
- exec `sbt "runMain gcd.VerilogGCD -- target-dir ./verilog` in the root of workspace

**What is the current behavior?**

`GCD.v` `GCD.fir` `GCD.anno.json` are generated in the root of workspace

exec `sbt "runMain gcd.VerilogGCD --help` show no help information, but elaborate design.

**What is the expected behavior?**

`GCD.v` `GCD.fir` `GCD.anno.json` are generated in `{workspace_root}/verilog`

In the doc:

> You can see additional options with
>
> ```bash
> bash> sbt 'runMain intro.HelloWorld --help'
> ```
>
> This will return a comprehensive usage line with available options.
>
> For example to place the output in a directory name buildstuff use
>
> ```bash
> bash> sbt 'runMain intro.HelloWorld --target-dir buildstuff --top-name HelloWorld'
> ```

**Please tell us about your environment:**

- version: chisel3 3.4.3, scala 2.12.13, sbt 1.5.5 (I didn't change build.sbt provided in chisel-template)
- OS: Ubuntu 20.04 in Win 10 wsl 2, x86_64

---

I wonder how to generate verilog into the target directory

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.