chipsalliance / chipsalliance/chisel
Cannot use `--target-dir` in `runMain`
- Dominant language
- Scala
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Description
**Type of issue**: bug report | documentation
**If the current behavior is a bug, please provide the steps to reproduce the problem:**
- Generate a chisel project via chisel-template
- Add these lines to GCD.scala
```scala
object VerilogGCD extends App {
(new chisel3.stage.ChiselStage).emitVerilog(new GCD())
}
```
- exec `sbt "runMain gcd.VerilogGCD -- target-dir ./verilog` in the root of workspace
**What is the current behavior?**
`GCD.v` `GCD.fir` `GCD.anno.json` are generated in the root of workspace
exec `sbt "runMain gcd.VerilogGCD --help` show no help information, but elaborate design.
**What is the expected behavior?**
`GCD.v` `GCD.fir` `GCD.anno.json` are generated in `{workspace_root}/verilog`
In the doc:
> You can see additional options with
>
> ```bash
> bash> sbt 'runMain intro.HelloWorld --help'
> ```
>
> This will return a comprehensive usage line with available options.
>
> For example to place the output in a directory name buildstuff use
>
> ```bash
> bash> sbt 'runMain intro.HelloWorld --target-dir buildstuff --top-name HelloWorld'
> ```
**Please tell us about your environment:**
- version: chisel3 3.4.3, scala 2.12.13, sbt 1.5.5 (I didn't change build.sbt provided in chisel-template)
- OS: Ubuntu 20.04 in Win 10 wsl 2, x86_64
---
I wonder how to generate verilog into the target directory
Contributor guide
Assessment
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