Chisel Doesn't Check Cross Module Refs to Memories

Chisel doesn't seem to apply the same checking for creating an mport that it does to reading the contents of a submodule.

Consider the following circuit:

```scala
class Bar extends MultiIOModule {
val mem = SyncReadMem(8, UInt(4.W))
}

class Foo extends MultiIOModule {
val bar = Module(new Bar)
bar.mem(0)
}
```

This will produce the following CHIRRTL:

```scala
circuit Foo :
module Bar :
input clock : Clock
input reset : Reset

smem mem : UInt<4> [8] @[main.scala 7:24]

module Foo :
input clock : Clock
input reset : UInt<1>

inst bar of Bar @[main.scala 11:19]
bar.clock <= clock
bar.reset <= reset
infer mport MPORT = mem[UInt<1>("h0")], clock @[main.scala 13:10]
```

This properly errors out in the Scala FIRRTL Compiler with `Undefined memory mem referenced by mport MPORT`. However, this type of usage is normally a Chisel-level error. Contrast the above with:

```scala
class Bar extends MultiIOModule {
val wire = WireInit(0.U(8.W))
}

class Foo extends MultiIOModule {
val bar = Module(new Bar)
bar.wire + 1.U
}
```

This produces an elaboration error of `operand is not visible from the current module`. I'd expect to get this error for the above memory case.

Runnable example of the first case showing the error: https://scastie.scala-lang.org/a8scMRY8SvKVzBO3ZPIeXw

**Type of issue**: bug report

**Impact**: no functional change

**Development Phase**: request

**Other information**

See above.

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

See above.

**What is the current behavior?**

See above.

**What is the expected behavior?**

See above.

**Please tell us about your environment:**

Chisel 3.4.3.

**What is the use case for changing the behavior?**

Catch bugs earlier.