chipsalliance / chipsalliance/chisel
ReplSeqMem does not generate memory replacement for cells with specified ReadFirst/WriteFirst
- Dominant language
- Scala
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- 14
Description
Hello,
**Type of issue**: bug report
**Impact**: API addition (no impact on existing code)
**Other information**
When SyncReadMem is created with ReadFirst or WriteFirst specified SyncReadMem is not replaced by ReplSeqMem. It works fine if left default: Undefined
1. SyncReadMem w/ ReadFirst or WriteFirst
2. Compile with ReplSeqMem
3. Expected behaviour memory replaced with macro and macro added to configuraiton file
4. Current behaviour memory is not replaced and nothing is generated in configuration file
chisel3 latest stable
(IDK if this needs to be reported to FIRRTL repo or here)
If reproduction repo is required write a message in here and I will create it.
Thanks,
Arman
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Assessment
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