Verilator does not output "EXPECT AT" type of logs like firrtl

**Type of issue**: bug report

**Impact**: unknown
Steps to reproduce:
Run anything that causes iotesters to fail expect

**What is the current behavior?**
No message on which cycle error happened and what was expected and what value got.
Verilator:
```
**skipped**
[info] [2.011] ReadShared (len=8) start: addr=0x068, lock=0
[info] [2.027] 8
[info] [2.139] Return dataReadShared (len=8) start: addr=0x068, lock=0
Enabling waves..
Exit Code: 0
[info] [2.211] Read address
[info] [2.217] RAN 87 CYCLES FAILED FIRST AT CYCLE 86
[info] CCXInterconnectTester:
[info] CCXInterconnect
[info] - should work very good (with verilator) *** FAILED ***
[info] false was not true (ccx_interconnect_tester.scala:1376)

```

**What is the expected behavior?**
Proper message like for FIRRTL:
```
**skipped*
ReadNoSnoop (len=0) start: addr=0x64
[info] [5.057] Starting read clean for 2 t=75
[info] [5.212] 8
[info] [5.553] start test_ReadClean_mbus_response, t=83
[info] [5.765] EXPECT AT 86 io_corebus_3_ar_ready got 0 expected 1 FAIL // <--------------------------------------------
test CCXInterconnect Success: 6208 tests passed in 92 cycles taking 6.485128 seconds

[info] [5.933] RAN 87 CYCLES FAILED FIRST AT CYCLE 86
[info] CCXInterconnectTester:
[info] CCXInterconnect
[info] - should work very good (with firrtl) *** FAILED ***
[info] false was not true (ccx_interconnect_tester.scala:1379)

```

**What is the use case for changing the behavior?**
Being able to use verilator while writing tests

Start by reproducing the failure through iotesters and compare the Verilator output with the FIRRTL example. Use ccx_interconnect_tester.scala at lines 1376 and 1379 as the reported failure points. Done means Verilator reports the failing cycle, signal, actual value, and expected value in an EXPECT AT-style message.

Written by the indexing model from the issue text.