Documentation/tutorial on integrating design with bus.

I struggle to find a documentation or tutorial on how to integrated the design with bus (such as AXI or Wishbone). I guess there must be one as Chisel claims to allow "SoC implementations.

By the way, is it possible to automatically generate control/status registers with Chisel?

No file, test, or entry point is named in the issue. Start by surveying existing Chisel SoC, AXI, and Wishbone integration documentation, then clarify whether the deliverable is a tutorial, control/status-register guidance, or both. Done means a newcomer can follow the documented integration path and find an answer about automatic register generation.

Written by the indexing model from the issue text.