Error info inconsistency among chisel3 and Chisel

I am reading thru the rocketchip code base, and found some possible dead code, the details are covered in another issue posted in rocketchip repo: https://github.com/chipsalliance/rocket-chip/issues/2835

According to https://github.com/chipsalliance/chisel3/issues/336#issuecomment-255287979, There are unbound type(chisel type), and boundtype(hardware) among the chisel data type. I read somewhere that inside the Bundle or Record(aggregate), the fields shoule only be unboundtype. So, IMHO, the Wire wrapper covered in this issue(https://github.com/chipsalliance/rocket-chip/issues/2835) is wrong(it is actually dead code contextually)
I wonder if my understanding to this is right?
Also, I wrote a snacky little test, and found some thing strange:
```

import Chisel.{Decoupled, DecoupledIO, Wire}
import Chisel._

class TLBundle() extends Record {
private val optA = None//Some (Decoupled(UInt(8.W)))
val a: DecoupledIO[UInt] = optA.getOrElse(Wire(Decoupled(UInt(8.W))))
val b: DecoupledIO[UInt] = Wire(Decoupled(UInt(8.W)))
val c: DecoupledIO[UInt] = Wire(Decoupled(UInt(8.W)))
val d: DecoupledIO[UInt] = Wire(Decoupled(UInt(8.W)))
val e: DecoupledIO[UInt] = Wire(Decoupled(UInt(8.W)))
override def cloneType: this.type = (new TLBundle).asInstanceOf[this.type ]
val elements =ListMap("e11" -> e, "d11" -> d, "c" -> c, "b" -> b, "a" -> a)
}

class TestIO extends Bundle{
val in = Flipped(new TLBundle())
val out = new TLBundle()
}

class Top extends Module {
val io = IO(new TestIO)
io.out <> io.in
}
```

Above code will throw following exception:

```

Elaborating design...
[error] scala.UninitializedFieldError: Uninitialized field: C:\D\chisel-example\chiselTest\src\main\scala\Hello.scala: 77
[error] ...
[error] at Top.io(Hello.scala:77)
[error] at Top.io(Hello.scala:76)
[error] at chisel3.internal.LegacyModule._io(RawModule.scala:211)
[error] at chisel3.internal.LegacyModule._compatIoPortBound(RawModule.scala:214)
[error] at Chisel.package$CompatibilityModule._compatAutoWrapPorts(compatibility.scala:326)
[error] at chisel3.internal.requireIsHardware$.apply(Binding.scala:14)
[error] at chisel3.Data.ref(Data.scala:478)
[error] at chisel3.WireFactory.apply(Data.scala:623)
[error] at chisel3.WireFactory.apply$(Data.scala:612)
[error] at Chisel.package$Wire$.apply(compatibility.scala:66)
[error] at TLBundle.$anonfun$a$3(Hello.scala:62)
[error] at scala.Option.getOrElse(Option.scala:189)
[error] at TLBundle.$anonfun$a$2(Hello.scala:62)
[error] at chisel3.internal.prefix$.apply(prefix.scala:49)
[error] at TLBundle.$anonfun$a$1(Hello.scala:62)
[error] at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:52)
[error] at TLBundle.(Hello.scala:62)
[error] at TestIO.$anonfun$in$1(Hello.scala:72)
[error] at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:52)
[error] at TestIO.(Hello.scala:72)
[error] at Top.$anonfun$io$2(Hello.scala:77)
[error] at chisel3.internal.prefix$.apply(prefix.scala:49)
[error] at Top.$anonfun$io$1(Hello.scala:77)
[error] at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:52)
[error] at Top.(Hello.scala:77)
[error] at Hello$.$anonfun$new$2(Hello.scala:81)
[error] ... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)

Process finished with exit code 0

```

However, if I switch the import declaration to `import chisel3._`, and run the exactly same code snippet, the error info is as follows:
```

Elaborating design...
[error] chisel3.package$RebindingException: Attempted reassignment of binding to DecoupledIO(Wire in Top)
[error] ...
[error] at Top.$anonfun$io$2(Hello.scala:77)
[error] at chisel3.internal.prefix$.apply(prefix.scala:49)
[error] at Top.$anonfun$io$1(Hello.scala:77)
[error] at chisel3.internal.plugin.package$.autoNameRecursively(package.scala:52)
[error] at Top.(Hello.scala:77)
[error] at Hello$.$anonfun$new$2(Hello.scala:81)
[error] ... (Stack trace trimmed to user code only, rerun with --full-stacktrace if you wish to see the full stack trace)

Process finished with exit code 0
```
Frankly speaking, I felt both the error infos are very unclear about the root cause of this error(Wire wrapper should be deleted). Is this an imperfection? But the chisel3's is apparently much better. I wonder what does `scala.UninitializedFieldError: Uninitialized field` error info mean in the first import Chisel._ situation. Which field is not initialized?
Also, in what situation should I import the Chisel._ instead of chisel3._? Is this what you called compatibility layer?
I felt like this is a chisel issue instead of rocktchip. So , I open this issue here, can anyone clarify this? Thanks for your hardwork
@jackbackrack @sdtwigg @ducky64 @jackkoenig