Use package names in generated Verilog modules

**Type of issue**: feature request

**Impact**: unknown, depending on the resulting API change

In Scala/Java land we use packages to minimize possible name clashing. However, these package names are dropped from the Verilog module names. Would be nice to keep them (e.g., module package_ClassName). This is especially useful for mixed-language projects (e.g., Chisel code is not the top-level).

No files or tests are named in the issue. Start by locating the Verilog module-name generation entry point and existing tests for generated names, then trace how Scala package names are discarded. Done means package-qualified module names are emitted without collisions and the resulting API or compatibility impact is covered by tests.

Written by the indexing model from the issue text.