chipsalliance / chipsalliance/chisel

Compatibility Chisel Top name error

Open
#1,862 0 comments 0 reactions 0 assignees View on GitHub
bug
Dominant language
Scala
Stars
4.8k
Forks
658
Avg merge
18h 59m
Merged PRs (30d)
14

Description

Here is the bug repetition repository:
https://github.com/sequencer/rc_topname_bug
CI should illustrate this error:
https://github.com/sequencer/rc_topname_bug/actions/runs/746420331
Reproduce on the local environment:
run with docker: `archlinux/archlinux:latest`
install dependencies: `pacman -Syu --noconfirm make parallel cmake ninja python mill dtc verilator git llvm clang lld`
repetition: `make patch; make test`

TestHarness io is wrong:
```
module TestHarness :
input clock : Clock
input reset : UInt<1>
output in_0_b_bits_io : {success : UInt<1>}
```
which should be
```
module TestHarness :
input clock : Clock
input reset : UInt<1>
output io : {success : UInt<1>}
```
I doubt the auto naming stack management exists some potential error, but failed to figure out.

**Type of issue**: bug report
**Development Phase**: request

Contributor guide

Open the contributing guide

Research direction

Start by cloning the linked rc_topname_bug reproduction and running `make patch; make test` in the specified Arch Linux Docker environment; compare the generated TestHarness interface with the expected `io` output. Use the linked CI run to confirm the failure and trace the auto-naming behavior responsible for `in_0_b_bits_io`; done means the generated interface matches the expected name and the reproduction passes.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Bug
Difficulty
4/5
Estimated time
3-5 days
Activity status
Stale
Clarity
Needs clarification
Newbie friendliness
25/100

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.