Verilog attribute annotations in modules are being lost when dedupping

**Type of issue**: bug report

**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
Here is an example where a Verilog attribute is being emitted correctly if only one module is instantiated and not emitted when there are two duplicate modules.
https://scastie.scala-lang.org/Quarky93/SIjXX7lgRj2Q3iS19PA0Cg/22

I believe this also happens for memory initialisation annotations where $readmemh is generated.

**What is the current behavior?**
Verilog attribute is emitted correctly if only one module is instantiated and not emitted when there are duplicate modules after deduplication.

**What is the expected behavior?**
Attribute annotations should be kept after deduplication.

**Please tell us about your environment:**
chisel 3.4.2