RegInit errors when passed a Bundle Literal

**Type of issue**: bug report

**Impact**: no functional change

**Development Phase**: request

**Other information**

Using Chisel v3.4.2

**If the current behavior is a bug, please provide the steps to reproduce the problem:**

https://scastie.scala-lang.org/4CDkXkNHQpKV7ItnPRtcvw

```scala
import chisel3._
import chisel3.experimental.BundleLiterals._

class MyBundle extends Bundle {
val a = UInt(8.W)
val b = Bool()
}

class Example extends MultiIOModule {
val in = IO(Input(new MyBundle))
val en = IO(Input(Bool()))
val out = IO(Output(new MyBundle))

// It works if you wrap the Bundle lit in WireInit
val r = RegInit((new MyBundle).Lit(_.b -> true.B))
when (en) {
r := in
}
out := r
}
```

**What is the current behavior?**

```
chisel3.internal.ChiselException: operand is not visible from the current module
```

**What is the expected behavior?**

This should work, and does if you wrap the Bundle Literal in `WireInit`

**What is the use case for changing the behavior?**

Fix a bug

Start with the linked Scastie reproduction and inspect how RegInit handles the Bundle literal created through BundleLiterals.Lit, comparing it with the WireInit-wrapped form. Done means the shown Chisel example elaborates without the “operand is not visible from the current module” exception and preserves the expected initialization behavior.

Written by the indexing model from the issue text.