[RFC] CDC library

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: proposal

For a PnR friendly RTL, I think we should start to consider how to add Clock-domain-checking library.
Here are my simple ideas to this problem.

for registers in the circuit, they have 4 types:
1. under a clock
1. under a clock and correspond synchronous reset
1. under a clock and full asynchronous reset
1. under a clock and asynchronous reset synchronous deassertion reset.
RTL of "full asynchronous" and "asynchronous reset synchronous deassertion" are same:
https://scastie.scala-lang.org/6HKMD9YbSxGeZxP0oroEtw

However a synchronizer should be implemented like this.
https://scastie.scala-lang.org/gAUzcR5iQXSCXVXwGgEATA

These two asynchronous reset have two types of reset, but a same chisel type.

Basically, my idea is annotate clock and reset and let FIRRTL transform to resolve and check them.
I wanna RFC for some comments on what to annotate, and what to check.
Here are something I can come up with:
1. annotate clock frequency.
2. annotate clock - synchronous reset relationship
3. annotate reset generation IO or Module.
4. annotate asynchronous type.
5. annotate false path(from register to register?)
6. annotate safe cross clock domain Module.(AsyncQueue, RationalQueue etc.)
7. check register under different clock are not crossing.
8. check register under same clock - synchronous reset pair are not crossing to other clock - synchronous reset pair.
9. check asynchronous resets are from a reset generation IO without passing any combinational path.

Output should be a set of annotations and can have a vendor specific Transform to generate SDC files.