chipsalliance / chipsalliance/chisel

only last register of ShiftRegister can be renamed by suggestName

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#1,722 3 comments 0 reactions 0 assignees View on GitHub
Dominant language
Scala
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Merged PRs (30d)
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Description

**Type of issue**: bug report
**Impact**: no functional change

**Development Phase**: request

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
https://scastie.scala-lang.org/BUm3SiiCTA6DRLi9b51YPQ

**What is the current behavior?**
`suggestName` only rename last register.

**What is the expected behavior?**
`suggestName` should rename all register generated by `ShiftRegister`

Contributor guide

Open the contributing guide

Research direction

Start with the linked Scastie reproduction and inspect the ShiftRegister implementation and its suggestName behavior. Confirm why only the final generated register is renamed; done means every register generated by ShiftRegister receives the suggested name without changing functionality.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
compilers
Issue type
Bug
Difficulty
3/5
Estimated time
1-2 days
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
35/100

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