RegInit(VecInit vs VecInit( ... RegInit

**Type of issue**: bug report | feature request | documentation | other enhancement
other enhancement

**Impact**: no functional change | API addition (no impact on existing code) | API modification | unknown
no functional change

**Development Phase**: request | proposal
request(?)
**Other information**

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
Using, for example,
val x = VecInit(Seq.fill(4) (RegInit(0.U(10.W))))
and then later updating like so:
x(2) := x(2) + 4.U
throws a combinational loop error pointing to this line.
However, having val x = RegInit(VecInit(Seq.fill(4) (0.U(10.W)))) doesn't have that problem.
**What is the current behavior?**
Throws a combinational loop error
**What is the expected behavior?**
FIRRTL/some other entity should identify that it's a syntax/style error, perhaps? Or at least suggest using an alternative like RegInit(VecInit instead of VecInit(...RegInit like with other cases
**Please tell us about your environment:**
- version: 3.3-SNAPSHOT
- OS: Linux oxygen 5.4.0-58-generic #64-Ubuntu SMP Wed Dec 9 08:16:25 UTC 2020 x86_64 x86_64 x86_64 GNU/Linux
**What is the use case for changing the behavior?**
Would save a lot of time in figuring out if it really is a combinational loop error as not everybody can go through the exhaustive process of familiarising themselves with the coding style/syntax thoroughly.

Start by reproducing the combinational-loop error with the VecInit(Seq.fill(4)(RegInit(...))) example and compare it with RegInit(VecInit(...)). Trace the FIRRTL diagnostic for this case; done means the problematic style is identified clearly or the diagnostic suggests the alternative without changing functional behavior.

Written by the indexing model from the issue text.