RefNotInitializedException when use switch

**Type of issue**: bug report | other enhancement

when I write MUX using switch block, one exception be thrown:
[info] firrtl.passes.CheckInitialization$RefNotInitializedException: : [module Mux4] Reference io is not fully initialized.
[info] @[Mux4.scala 43:12 Mux4.scala 46:12 Mux4.scala 49:12 Mux4.scala 52:12] : io.y <= mux(_T, io.a, mux(_T_1, io.b, mux(_T_2, io.c, mux(_T_3, io.d, VOID)))) @[Mux4.scala 43:12 Mux4.scala 46:12 Mux4.scala 49:12 Mux4.scala 52:12]

But I think there is no wire not connect, why it throw RefNotInitializedException, also why chisel try to use so much MUXs?
Is it a bug of chisel?

Here is my code:
```
class Mux4 extends Module {
val io = IO(new Bundle {
val a = Input(UInt(1.W))
val b = Input(UInt(1.W))
val c = Input(UInt(1.W))
val d = Input(UInt(1.W))
val sel = Input(UInt(2.W))
val y = Output(UInt(1.W))
})
switch(io.sel) {
is("b00".U) {
io.y := io.a
}
is("b01".U) {
io.y := io.b
}
is("b10".U) {
io.y := io.c
}
is("b11".U) {
io.y := io.d
}
}
}
```
Chisel version I use is 3.3.1

when I add the default value, it works. But isn't it unnecessary?
```
io.y := 0.U
switch(io.sel) {
is("b00".U) {
io.y := io.a
}
is("b01".U) {
io.y := io.b
}
is("b10".U) {
io.y := io.c
}
is("b11".U) {
io.y := io.d
}
}
```