Unexpected behaviour of connections for `Reg` defined within `when` context

**Type of issue**: bug report
**Impact**: unknown
**Development Phase**: request
**Other information**: see example below

**If the current behavior is a bug, please provide the steps to reproduce the problem:**
Simple code example of a `Reg` defined and connected within a `when` context:

```scala
@chiselName
class BadWhenContext() extends MultiIOModule {
val en = IO(Input(Bool()))
val in = IO(Input(UInt(3.W)))
val out = IO(Output(UInt(3.W)))

val rin = Reg(chiselTypeOf(in))
val rout = Reg(chiselTypeOf(in))


when(en){
i := in
val inner1 = Reg(chiselTypeOf(i))
inner1 := i + 1.U
rout := inner1
}
out := rout
}
```
**What is the current behavior?**
`when` context is ignored for embedded `Reg` connections as shown below (trimmed verilog):
```verilog
reg [2:0] rin;
reg [2:0] rout;
reg [2:0] inner1;
assign out = rout;
always @(posedge clock) begin
if (en) begin
rin <= in;
end
if (en) begin
rout <= inner1;
end
inner1 <= rin + 3'h1; // expecting this statement to also be surrounded with its own if(en) block
end
```
**What is the expected behavior?**
`when` context applied to connections of embedded `Reg`, such as below (trimmed verilog):
```verilog
reg [2:0] rin;
reg [2:0] rout;
reg [2:0] inner1;
assign out = rout;
always @(posedge clock) begin
if (en) begin
rin <= in;
end
if (en) begin
rout <= inner1;
end
if (en) begin
inner1 <= rin + 3'h1;
end
end
```
**Please tell us about your environment:**
- version: `3.4-20200728-SNAPSHOT`
- OS: `Darwin 17.7.0 Darwin Kernel Version 17.7.0: Mon Aug 31 22:11:23 PDT 2020;`

**What is the use case for changing the behavior?**
Consistency: why isn't the when context applied to registers defined within himself?

Note: the actual use case is to be able to surround with a `when` context a function declaring and using `Reg` within its body.

The issue names no repository files or tests; start by reproducing the BadWhenContext example and inspecting its generated Verilog. Compare the handling of the embedded inner1 register with the expected output, and consider the work complete when its update is guarded by the surrounding when(en) context.

Written by the indexing model from the issue text.