[RFC] Warning/Error if CDC not managed correctly

Question/request asked first [on Stackoverflow](https://stackoverflow.com/questions/55569545/is-there-a-way-to-warn-wrong-clock-domain-crossing-in-chisel3).

**Type of issue**: feature request
**Impact**: API modification
**Development Phase**: request

**What is the current behavior?**

Currently, it's possible to manage different Clock domains with Chisel3. But if we need to read/write a signal through two different clock domains it's important to manage metastability (with dual d-latch, asynchronous fifo, ...).

If we don't manage this cross-clock-domain Chisel will not warn or error about it.

**What is the expected behavior?**

If we don't says explicitly to Chisel that we managed this crossing. The behavior expected should be in minimum to warn, maybe to generate an error.

**What is the use case for changing the behavior?**

In the wiki [example](https://github.com/freechipsproject/chisel3/wiki/Multiple-Clock-Domains):

```
class MultiClockModule extends Module {
val io = IO(new Bundle {
val clockB = Input(Clock())
val resetB = Input(Bool())
val stuff = Input(Bool())
})

// This register is clocked against the module clock.
val regClock = RegNext(io.stuff)

withClockAndReset (io.clockB, io.resetB) {
// In this withClock scope, all synchronous elements are clocked against io.clockB.
// Reset for flops in this domain is using the explicitly provided reset io.resetB.

// This register is clocked against io.clockB.
val regClockB = RegNext(io.stuff)
}

// This register is also clocked against the module clock.
val regClock2 = RegNext(io.stuff)
}
```

We could add a function named cdc() for example to signal Chisel that we know that signal is crossing clock domain :
If we write this we will have an error/warning :

val regClockB = RegNext(io.stuff)

And to delete the error we could do :

val regClockB = cdc(RegNext(io.stuff))

With maybe adding the names of clocks domains implied in arguments ?