chipsalliance / chipsalliance/chisel

Bit Slice with (start, length) instead of (start, end)

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#1,081 1 comment 0 reactions 0 assignees View on GitHub
Dominant language
Scala
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Merged PRs (30d)
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Description

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Development Phase**: request

**Other information**

#1079 is a fix for zero-width wires in bundles breaking `asTypeOf`. It is an instance of a more general problem: zero-width wires often break assumptions about widths. @ducky64 and @aswaterman noted that slicing with (start, length) is a clean way of dealing with zero-width wires and is also generally useful.

I think we could make something like `1 +: 3` work via implicits to produce a slice object, so we'd have
```
def apply(hi: Int, lo: Int) // exists now
def apply(slice: Slice) // new

implicit class SliceMaker(start: BigInt) {
def this(start: Int)
def +:(that: BigInt): Slice
def +:(that: Int): Slice
// possible to add other ways of slicing, if compatible with backend
}
```

It seems to me that with the way firrtl works it would be hard to do general slices, but (start, length) seems compatible with the way firrtl works so I don't think it needs any special backend support.

Contributor guide

Open the contributing guide

Research direction

Start by locating the existing apply(hi, lo) API and reviewing issue #1079 for the zero-width-wire context. Then trace how slicing is represented through FIRRTL and assess the proposed SliceMaker and Slice entry points. Done means a (start, length) slice API is defined without breaking existing slicing or requiring unsupported backend behavior.

Written by the indexing model from the issue text.

Assessment

Tech stack
scala
Domain
backend-api-design, compilers
Issue type
Feature
Difficulty
5/5
Estimated time
Over a week
Activity status
Stale
Clarity
Mostly clear
Newbie friendliness
30/100

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