chipsalliance / chipsalliance/chisel
[RFC] Add standalone asyncqueue librarys to experimental.
- Dominant language
- Scala
- Stars
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- Avg merge
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- Merged PRs (30d)
- 14
Description
**Type of issue**: feature request
**Impact**: API addition (no impact on existing code)
**Development Phase**: proposal
**What is the use case for changing the behavior?**:
After `withClockAndReset` API added, There are possibility to enhance multi-clock support.
However if we need register pass between different clocks domains, we still need to include Crossing API in [rocket-chip](https://github.com/freechipsproject/rocket-chip/), or use the lightweight [asyncqueue](https://github.com/ucb-bar/asyncqueue) package.
Is it possible that after [PR](https://github.com/ucb-bar/asyncqueue/pull/3) merged, create some crossing API to provide multi-clock register visit by which.
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