Modifying the name of the module that comes from Chisel Library.

**Type of issue**: other enhancement

**Impact**: API addition (no impact on existing code)

**Development Phase**: proposal

**What is the current behavior?**

If I create a Module which from Chisel Library, for example, Queue, there will be a verilog module named Queue. In the meantime, if another person also creates a Queue, my Queue will conflict with his because two modules have the same name. But I can't modify the name of Queue dynamically.

**What is the expected behavior?**

I want to generate modules of the Chisel Library with custom names. Maybe a better desiredName method will work. However, I can only do it like this:
```
class MyQueue[T <: Data](gen: T, entries: Int) extends Queue(gen, entries)
val mq = Module(new MyQueue(g, e))
```

**Please tell us about your environment:**
- version: `3.2-SNAPSHOT`
- OS: `Ubuntu 16.04`

**What is the use case for changing the behavior?**
Nothing.

Start by reviewing the Chisel Library Queue example, the Module construction shown in the issue, and the desiredName API to understand how generated Verilog module names are selected. Trace the existing naming behavior and decide how custom names should work for library modules; done means a documented API and coverage for conflicting module names.

Written by the indexing model from the issue text.