chipsalliance / chipsalliance/chisel

API supports for ValidIO

Open
#1,055 0 comments 0 reactions 0 assignees View on GitHub
Dominant language
Scala
Stars
4.8k
Forks
658
Avg merge
18h 59m
Merged PRs (30d)
14

Description

**Type of issue**: feature request

**Impact**: API addition (no impact on existing code)

**Description**
API
https://github.com/freechipsproject/chisel3/blob/master/src/main/scala/chisel3/util/Valid.scala
1. Add end, noenq method for **Valid** (similar to **EnqIO**)
2. Add bulk connection between **Valid** and **EeqIO** (connect the valid and bits)

Because there is no such supports, codes get longer like this,
```scala
import chisel3._
import chisel3.util.{Valid, DeqIO, EnqIO}

class Test extends Module {
val io = IO(new Bundle{
val in = DeqIO(UInt(8.W))
val out = EnqIO(UInt(8.W))
})

val out_reg = RegInit(
0.U.asTypeOf(new Valid(UInt(8.W)))
)

//io.out <> out_reg
io.out.valid := out_reg.valid
io.out.bits := out_reg.bits

when(io.in.valid && io.out.ready) {
//out_reg.enq(io.in.deq())
out_reg.valid := true.B
out_reg.bits := io.in.deq()
}
.otherwise {
io.in.nodeq()
//out_reg.noenq()
out_reg.valid := false.B
out_reg.bits := DontCare
}
}

object Test extends App {
chisel3.Driver.execute(args, () => new Test)
}
```
3. Is there better way(than above) to create out_reg as RegInit so that valid is false ?

Thanks !

Contributor guide

Open the contributing guide

Assessment

This issue has not been assessed yet.

Get new issues in your inbox

A short digest of beginner-friendly GitHub issues.