chipsalliance / chipsalliance/chisel
Mismatch between wiki saying bitwise reductions work on SInts and implementation which does not
- Dominant language
- Scala
- Stars
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- Forks
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- Avg merge
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- Merged PRs (30d)
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Description
h/t @redpanda3 for noticing the mismatch
**Type of issue**: bug report | documentation
**Impact**: no functional change | API addition (no impact on existing code)
**Development Phase**: request
**Other information**
**What is the current behavior?**
Bitwise reduction operators are only defined on `UInt`, **not** on `SInt`
**What is the expected behavior?**
This Chisel wiki says they're defined on both `UInt` and `SInt`:
https://github.com/freechipsproject/chisel3/wiki/Builtin-Operators
**What is the use case for changing the behavior?**
I'm not sure if the behavior should change or if the documentation should change. I suspect the operators are only defined on `UInt` for a reason, and while my intuition is that `andR` and `orR` are fine on `SInt`s, `xorR` seems like it could interact in surprising ways with width inference.
I just wanted to make sure we fix the mismatch.
Contributor guide
Research direction
Start by comparing the Builtin-Operators wiki entry with the implementation of bitwise reduction operators for UInt and SInt. Determine whether the documented behavior or the implementation is authoritative, then update the relevant documentation or behavior so they agree; verify that the mismatch is resolved.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- documentation
- Issue type
- Documentation
- Difficulty
- 3/5
- Estimated time
- 1-2 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 35/100