chipsalliance / chipsalliance/chisel-template
Too much magic ;-)
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Description
Dear all,
the template worked as described, but for my feeling there is too much magic going on to understand a proposed Chisel project structure. What is 'sbt test' doing? Executing some Scala code in a path that has two times 'test' in the path? There is no main in the Scala/Chisel code. Is this Scala/sbt convention?
In the GCD tester I see two nested loops that should result in 100 tests, - what is the notion of SETP n -> m?
Then some magic invokes verilator and a a C++ compiler and tests run again. Are these now Verilog tests? The same thing as before? What was that before?
Sorry for those many questions, just want to get an idea on the design and test flow of Chisel 3 ;-)
Cheers,
Martin
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