chipsalliance / chipsalliance/chisel-template
No way to generate VCD files
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Description
The chisel-template compile and emits SystemVerilog as expected. The only problem is to generated the vcd (or fst) files. I read that this is automatically done but the vcd file is not generated.
I found that there's a function emitVcd but don't know where to apply it.
Any help would be appreciated.
Thanks
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