Modeling subregister aliasing

I’m experimenting with using regalloc2 for a cranelift backend targeting a old Z80 8-bit CPU with hierarchical registers —
where two small registers can form one larger register, and vice versa:

B + C = BC (16-bit)
D + E = DE (16-bit)
H + L = HL (16-bit)

Here’s the challenge:

Some 16-bit instructions can use either BC or DE.
When BC is used, both B and C become clobbered.
When DE is used, D and E are clobbered instead.

The 8-bit registers are individually addressable, but they also participate in 16-bit operations as pairs.

The problem is that regalloc2 assumes all physical registers in a class are disjoint,
and clobber sets must be fixed before allocation.
That makes it unclear how to express a relationship like “BC aliases both B and C” or “writing BC invalidates B and C.”

LLVM handles this using register units and subregisters, where overlapping registers share “register units”
and the allocator tracks partial definitions and interference on that level.
regalloc2, however, currently has no notion of aliasing or register overlap.

So I’m wondering:

Is there any way to model such subregister aliasing with the current regalloc2 API?

Would it make sense to support aliasing PRegs or register subsets (similar to LLVM’s register units / subregister indices)?

Or is the current expectation that these aliasing relationships be handled entirely outside the allocator,
e.g. by inserting explicit moves, using fixed constraints, or splitting live ranges manually?

Commencez par lire l'API actuelle de regalloc2 autour de PRegs, des classes de registres physiques et des ensembles de clobber, puis comparez-la au modèle LLVM des register-units et des subregisters. Le travail est terminé lorsqu'il est établi si l'aliasing peut être représenté, ou qu'une approche prise en charge en dehors de l'allocator est documentée, comme des constraints fixes, des moves explicites ou le découpage des live-ranges.

Rédigé par le modèle d'indexation à partir du texte de l'issue.