Limit operand to a set of physical registers

It seems like there are currently two options when expressing which registers an `Operand` can use:

* use `reg_def`/`reg_use`/..., in this case the operand can be allocated to any physical register.
* use `reg_fixed_def`/`reg_fixed_use`, in this case the operand can only be a single physical register.

This does not seem to cover the case where only of a limited set of physical registers can be used as an operand.

This is often the case on x86 (32-bit), where some of the general purpose registers don't expose their lower 8 bits as a pseudoregister. This means that `setcc` and other instructions dealing with a byte can only use the first 4 registers, not eg. `esi`.

My current workaround is to always use fixed operands for these instructions, but that is a bit too limiting. The other solution is to completely remove the additional registers from the `MachineEnv`, but that has even bigger drawbacks. Is there a better solution? It seems none of the ISAs supported by `wasmtime` have this issue, so I can't steal any ideas there.

Start by reviewing the Operand constraint forms (`reg_def`, `reg_use`, `reg_fixed_def`, and `reg_fixed_use`) and how MachineEnv represents physical registers. Compare the x86 32-bit byte-register limitation described for setcc with the existing supported ISAs. Done means a bounded set of physical registers can be expressed and its allocation behavior is covered by tests.

Written by the indexing model from the issue text.