BUG: samd51j19 incorrect NVIC Priority levels (is 2, should be 3)

In the process of debugging a samd51j19 based system (Adafruit Feather Express M4) I noticed that the __NVIC_PRIO_BITS defined in the file CMSIS/Device/ATMEL/samd51/include/samd51j19a.h is (incorrectly) set to 2.

The official Microchip data sheet "SAM D5x/E5x Family Data Sheet (2019)" section 10.1.3 (pg 62) shows the number of priority levels is 3. Hence I believe the include file is wrong, and the definition should be:

`#define __NVIC_PRIO_BITS 3 /*!< Number of bits used for Priority Levels */`

On my physical devices, there certainly are 3 priority levels. Trying to run FreeRTOS, where 3 bits are used, on the same platform uncovered this. Using the CMSIS __NVIC functions to set priorities of interrupt handlers causes some challenges as you need to use levels numerically at or above 5 (101) for handlers calling into FreeRTOS -- and only one level (6) can effectively be assigned through the CMSIS functions (11...... -> 110.....).

Before/in parallel with creating a pull request, I wanted to check for any obvious things I may have missed?

Beginne in CMSIS/Device/ATMEL/samd51/include/samd51j19a.h und vergleiche __NVIC_PRIO_BITS mit Abschnitt 10.1.3 des SAM D5x/E5x Family Data Sheet (2019). Die Aufgabe ist erledigt, wenn der Header die dokumentierten drei Prioritätsbits meldet und die Änderung anhand des beschriebenen CMSIS- und FreeRTOS-Prioritätsverhaltens überprüft ist.

Vom Indexierungsmodell aus dem Issue-Text verfasst.