Testbench required for roundlast.sv

# Description
Add a testbench for `roundlast.sv` to validate it's functionality. Please refer to [this](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) for a tutorial on writing a testbench.

# Notes:
- You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

Start by reading roundlast.sv and the linked SystemVerilog testbench tutorial. Add a testbench that exercises the module and checks its behavior, reporting any bugs found. Done means roundlast.sv functionality is validated; coverage reports, randomized testing, and self-assertion tests are optional enhancements mentioned in the issue.

Scritto dal modello di indicizzazione a partire dal testo della issue.