Testbench required for aes_main.sv

# Description
Add a testbench for `aes_main.sv` to validate it's functionality. Please refer to [this](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) for a tutorial on writing a testbench.

# Notes:
- You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.

Read aes_main.sv first and use the linked SystemVerilog testbench tutorial as the starting point. Create a testbench that validates the module's functionality, with coverage, randomized testing, and self-assertion checks as possible extensions, and report any bugs found.

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