acmpesuecc / acmpesuecc/aes-128-sysverilog-riscv
Testbench required for aes_main.sv
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Bounty: 25
documentation
enhancement
- 主要语言
- SystemVerilog
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- 2
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描述
# Description
Add a testbench for `aes_main.sv` to validate it's functionality. Please refer to [this](https://www.chipverify.com/systemverilog/systemverilog-simple-testbench) for a tutorial on writing a testbench.
# Notes:
- You are eligible to get brownie points if you report back bugs with the module, add coverage reports, randomized testing and self-assertion tests.
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