Graphic visualization of CHIP-8

While testing our RTL design it only gives output of functionality of our CHIP-8 system and not graphical visualization of it.

You need to compile verilog code (RTL design) into a C++ model using verilator and then build a graphical frontend (of working display) using RayLib.

Tasks:
> 1. Compile the RTL design into a C++ model using verilator
> 2. build a graphical frontend using RayLib
> 3. The goal is to create a C++ model which simulates RTL design and renders into a window.