RAM_STYLE should be ULTRA instead of URAM

CRITICAL WARNING: [Netlist 29-72] Incorrect value 'URAM' specified for property 'RAM_STYLE'. Expecting type 'enum' with possible values of 'auto,block,distributed,register,registers,ultra'.

This is using Vivado 2019.1

Look for RAM_STYLE attributes in the VHDL source files, likely in entity or architecture declarations. The value 'URAM' needs to be changed to 'ultra'. Search for 'RAM_STYLE' or 'URAM' in the project. After making the change, verify by checking Vivado synthesis reports for the corrected warning.

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