Add custom address width feature

Currently, the width of the address field for the AXI4-lite aw/ar channels are fixed at 32-bits.

For some use-cases, it is desirable if we could set the address width to something else.

From a quick scan of the specification, there seems to be no restrictions on the AXI4 address width.

The issue is about modifying the AXI4-lite address width in the VHDL code generator. Start by examining the code that generates the aw/ar channels, likely in the core generator modules. Look for where the address width is currently hardcoded to 32 bits. Understand the AXI4 specification to ensure changes comply. Testing will involve generating VHDL with different address widths and verifying the output.

Written by the indexing model from the issue text.