Atomic access to multi-block registers - holding register documentation

In [Atomic access to multi-block registers](https://abs-tudelft.github.io/vhdmmio/fieldconfig.html#atomic-access-to-multi-block-registers) you state:

> The advantage of sharing holding registers is that it reduces the size of the address decoder and read multiplexer; many addresses taking data from the same source is advantageous for both area and timing. The primary disadvantage is that it only works properly when the blocks are accessed sequentially and completely. It is up to the bus master to enforce this; if it fails to do so, accesses may end up reading or writing garbage. You can therefore generally NOT mix purely AXI4L multi-master systems with multi-block registers.

I am not sure you are correct here. With logical registers wider than the data bus width you still have multiple addresses, which you present, for example, here [bitrange](https://abs-tudelft.github.io/vhdmmio/fieldconfig.html#bitrange). The required address space size is not smaller because of the holding register, so how can it affect the address decoding logic? I think the only resource utilization you reduce by sharing the snapshot/shadow register (you call it holding register) is the number of flip flops required for logical registers wider than the data bus width.

Review the documentation sections on atomic access and bitrange. Examine the VHDL generator code for address decoding and holding register logic. Understand the AXI4-lite protocol and how multi-block registers are implemented. The goal is to clarify the resource trade-offs in the documentation.

Written by the indexing model from the issue text.