Improper dependency detection for some VHDL constructs

vhdeps' define/use matching is currently very simplistic, perhaps overly. For instance, it doesn't detect the following properly:

- components that are defined without the optional "is" keyword (there may be more like this)
- usage of components that don't have a port or generic map
- any recognized construct embedded in a string
- ...?

This all has to do with the fact that vhdeps' matching is entirely context-insensitive. For instance, without context sensitivity, component usage like above would require matching anything of the form `: ;`, which leads to a lot of false positives, for instance in signal declarations. To handle this properly, vhdeps' matcher would need to be aware of where blocks start and end at least.

vhdeps also doesn't currently support configurations, multiple architectures per entity, etc. in any way, mostly because I've never used them personally and have rarely seen them be used in the FPGA world.

The issue describes limitations in vhdeps' dependency detection for VHDL constructs like components without 'is', missing port/generic maps, and strings. Start by examining the parsing logic in the codebase to understand the current context-insensitive matching. Look for files handling VHDL syntax analysis and dependency graph generation. Testing changes will require understanding VHDL semantics and the project's test suite.

Rédigé par le modèle d'indexation à partir du texte de l'issue.