abs-tudelft / abs-tudelft/fletcher

Wrap AxiTop into an AxiTopSim for simulation

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enhancement fletchgen
主要語言
VHDL
星號
235
分支
30
PR 合併指標
30 天內沒有已合併 PR

描述

Currently the AXI top-level output of Fletchgen using --axi doesn't provide a simulation like the simulation top-level that it can generate using the --sim flag.

It would be nice to just wrapception the AXI top into a simulation top level, so the same simulation capabilities of the normal simulation top-level become available to the AXI top-level as well, testing the AXI top-level itself in the meanwhile for all different codegen tests.

This would also enable the possibility of adding a protocol checker on the axi-simulation top level.

Alternatively we could just make the simulation top-level always instantiate the AXI top wrapper.

貢獻指南

開啟貢獻指南

研究方向

Look at the Fletchgen codebase for the --axi and --sim flag implementations. Understand how the AXI top-level and simulation top-level are currently generated. The task is to create an AxiTopSim wrapper that instantiates the AXI top, enabling simulation capabilities and possibly adding a protocol checker. Start by examining existing test structures and simulation top-level generation code.

由索引模型根據 Issue 內容生成。

評估

領域
tooling
Issue 類型
功能
難度
3/5
預估耗時
1-2 天
活躍度
停滯
描述清晰度
基本清楚
新手友好度
45/100

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