[Rev 3] SPI Hardware NSS Pulse config issue

Version/Project: Flight Computer rev3

Describe the bug
Currently, SPI1 (IMU) and SPI3 (LoRa) are configured in CubeMX to use Hardware NSS management.
Looking at main.c, this results in the following configurations:

• hspi.Init.NSS = SPI_NSS_HARD_OUTPUT;
• hspi.Init.NSSPMode = SPI_NSS_PULSE_ENABLE;

Given LoRa and IMU approach to DMA w.r.t. how Chip Select is handled, current .ioc NSS Pulse Mode automatically drives the Chip Select line HIGH for one clock cycle between every single transmitted byte. Respective DMA implementations were intended to follow datasheet guidelines for each developed file:

• The LSM6DSV320X (IMU) datasheet requires CS to be held low for the entire duration of a multi-byte FIFO read.
• The RFM95 (LoRa) datasheet (Page 75) explicitly states: "The NSS pin goes low at the beginning of the frame and stays low between each byte."

Because of this hardware pulsing, we cannot use DMA to burst-read the IMU or LoRa FIFOs. The peripherals will see the CS pulse, assume the transaction was aborted, and return garbage data.

Luckily, this is an easy fix to be implemented/considered during integration phases of drivers. It is simple .ioc edit. Only holding off this personally b/c aforementioned integration concerns.

1. Connectivity -> SPI1 and SPI3.
2. Change Hardware NSS Signal to Disable.
3. In the Pinout View, make physical pins currently assigned to the IMU and LoRa Chip Selects and change them to standard GPIO_Output.
4. In System Core -> GPIO, configure these two pins as:
   • Output Level: High (to keep the chips off at boot)
   • Mode: Output Push Pull
   • Pull-up/Pull-down: Pull-up
   • Maximum output speed: Very High

This will return Init.NSS to SPI_NSS_SOFT in main.c, allowing driver callbacks (HAL_GPIO_WritePin) to properly hold the Chip Select low during multi-byte DMA transfers.

To Reproduce
Not applicable

Expected behavior
Prevent junk data from false Chip Select config

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Additional context
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Points of Contact
@MasterUser43
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