SpinalHDL / SpinalHDL/VexRiscv
Axi4Crossbar
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Description
Can Axi4Crossbar connect AXI ports from different clock domains?
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
The issue asks whether Axi4Crossbar can connect AXI ports from different clock domains. Start by locating Axi4Crossbar and reviewing how its ports handle clock domains. Done would be a confirmed capability answer or a clearly scoped change requirement, but no file or test is named.
Written by the indexing model from the issue text.
Assessment
- Domain
- embedded-iot
- Issue type
- Feature
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100