OpenXiangShan / OpenXiangShan/ChiselIOPMP
Register Map and Fields diverge from the latest IOPMP Spec (v0.8.2, 2026)
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- Dominant language
- Scala
- Stars
- 3
- Forks
- 3
- Avg merge
- 6m
- Merged PRs (30d)
- 1
Description
The current ChiselIOPMP RTL (specver = 8) does not match the latest RISC-V IOPMP spec (v0.8.2).
Reference: https://github.com/riscv-non-isa/riscv-iopmp/blob/e786122b6f0c9bbb8d98f8450e9305ffeeed5aa8/chapter4.adoc?plain=1#L78
This issue was detected by my checking tool, spechunter reports
Just wanted to check if syncing with the v0.8.2 spec is currently on your roadmap. Please feel free to correct me or simply close this issue if I missed any context regarding your development plans!
Thanks
Contributor guide
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by comparing the current ChiselIOPMP RTL (specver = 8) with chapter4 of the referenced RISC-V IOPMP v0.8.2 specification, using the spechunter report as a checklist. Identify the register-map and field differences; done means the RTL matches v0.8.2 and the reported discrepancies are resolved.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot, security
- Issue type
- Feature
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Active
- Clarity
- Needs clarification
- Newbie friendliness
- 35/100