OpenXiangShan / OpenXiangShan/ChiselAIA
【目前IMSIC与CPU交互接口，建议寄存输出】
Open
Nobody has claimed this yet.
- Dominant language
- Scala
- Stars
- 13
- Forks
- 7
- PR merge metrics
- No merged PRs in 30d
Description
目前看到，IMSIC与CPU的交互接口，尤其是输出信号，为组合逻辑输出的（与CSR交互的读数据，illegal，pending, topei），未寄存输出，由于CPU高频，时序收敛上存在一定的风险。
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the IMSIC–CPU interaction interface and the CSR read-data, illegal, pending, and topei output signals, then inspect how this design handles timing and registered outputs. Done means the requested outputs are registered in a way that addresses the stated high-frequency timing risk without changing their intended interface behavior.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Refactor
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 38/100