OpenXiangShan / OpenXiangShan/ChiselAIA
【时钟域及组件划分】
Open
Nobody has claimed this yet.
- Dominant language
- Scala
- Stars
- 13
- Forks
- 7
- PR merge metrics
- No merged PRs in 30d
Description
IMSIC控制器，包括两部分：1.总线转成reg部分，2.CSR处理部分。后者与CPU交互，时钟上与CPU CLOCK一致。前者总线部分逻辑，建议使用低频时钟。并且，两部分逻辑，作为两个小组件，分别以两个文件来交付。后端摆放，也可以按照时钟域来摆放（目前昆明湖是这个思路），异步处理逻辑，若涉及FIFO处理，需要分成两个半桥。
Contributor guide
No contributing guide indexed for this repository
First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the IMSIC controller and its current bus-to-register and CSR-processing logic. Separate these into two small components and files, with the CSR side using the CPU clock and the bus side using a lower-frequency clock. Review any asynchronous FIFO paths for the required split-bridge handling.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Refactor
- Difficulty
- 5/5
- Estimated time
- Over a week
- Activity status
- Stale
- Clarity
- Mostly clear
- Newbie friendliness
- 30/100