OpenXiangShan / OpenXiangShan/ChiselAIA
【csr_wdata_vld 时序是怎样的？】
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- Dominant language
- Scala
- Stars
- 13
- Forks
- 7
- PR merge metrics
- No merged PRs in 30d
Description
IMSIC接口时序上，南湖与昆明湖项目是否是一致的？现在看到南湖IP：i_csr_wdata_vld与i_csr_addr_vld同时存在，昆明湖只有一个vld，两者时序是是否一致？
若两个信号的时序是一样的，如下内部有一块是illegal的访问，预期会有bug：
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First steps
- Read the whole issue, then the project's contributing guide.
- Comment on the issue to say you are picking it up — it saves two people doing the same work.
- Fork the repository and make your change on a branch.
- Open a pull request that references the issue number.
Research direction
Start by locating the IMSIC interface and the handling of i_csr_wdata_vld and i_csr_addr_vld in the ChiselAIA sources. Compare the Nanhu timing, where both signals exist, with the Kunminghu single-vld timing, then inspect the illegal-access case illustrated in the attached images; done means the timing relationship and any resulting bug are documented or corrected.
Written by the indexing model from the issue text.
Assessment
- Tech stack
- scala
- Domain
- embedded-iot
- Issue type
- Bug
- Difficulty
- 4/5
- Estimated time
- 3-5 days
- Activity status
- Stale
- Clarity
- Needs clarification
- Newbie friendliness
- 25/100