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CHERIoT-Platform

8 indexed repositories · View on GitHub

cheriot-rtos
The RTOS components for the CHERIoT research platform

C++ · 167 stars
cheriot-sail
Sail code model of the CHERIoT ISA

TeX · 50 stars
cheri-rust
🍒 Rust - Experimental port of Rust to CHERI architectures

Rust · 14 stars
riscv_trace_debugger
Tool for debugging RISC-V execution traces with a real debugger

Rust · 11 stars
network-stack

C++ · 9 stars
cheriot-demos
Space for all of the CHERIoT demos that people have been building for various purposes

C · 8 stars
book
The public drafts of the CHERIoT Programmers' Guide

Lua · 8 stars
devcontainer
Scripts for creating the CHERIoT dev container

Dockerfile · 5 stars

Open All

173 open issues indexed

The compartment switcher holds interrupts disabled for too long Open

CHERIoT-Platform/cheriot-rtos#47 · 0 comments · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Should interrupts be enabled when the scheduler yields? Open

CHERIoT-Platform/cheriot-rtos#56 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Create sub-quotas for allocation capabilities Open

good first issue

CHERIoT-Platform/cheriot-rtos#140 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
MMIO regions are artificially constrained to 2^24 bytes Open

CHERIoT-Platform/cheriot-rtos#182 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add a compartment initalisation framework Open

CHERIoT-Platform/cheriot-rtos#275 · 16 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Update claims documentation Open

CHERIoT-Platform/cheriot-rtos#281 · 0 comments · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Explore alternate build systems Open

CHERIoT-Platform/cheriot-rtos#304 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Allocator needs more aggressive fuzzing Open

CHERIoT-Platform/cheriot-rtos#305 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
stdio/stderr UART initialization Open

CHERIoT-Platform/cheriot-rtos#317 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Token APIs have confusing names Open

CHERIoT-Platform/cheriot-rtos#319 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Libraries should be compiled with CHERIOT_NO_AMBIENT_MALLOC Open

CHERIoT-Platform/cheriot-rtos#322 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Allocator: apply violence to free up some bits in the chunk header Open

CHERIoT-Platform/cheriot-rtos#332 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Future small tweaks to switcher? Open

CHERIoT-Platform/cheriot-rtos#334 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Performance monitoring API Open

enhancement

CHERIoT-Platform/cheriot-rtos#367 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Networking: Consolidate waits/delays. Open

CHERIoT-Platform/book#18 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Typo: error example references `monotonic`, which was not introduced yet Open

CHERIoT-Platform/book#78 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Update minimum project boilerplate Open

CHERIoT-Platform/book#80 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Add allocator-capability permission documentation Open

CHERIoT-Platform/book#82 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Document the newer locks Open

CHERIoT-Platform/book#83 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Additional layer(s) with prepackaged RTOS? Open

CHERIoT-Platform/devcontainer#34 · 1 comment · 0 reactions · 1 assignee · Indexed Sep 14, 2026
Add definition of CHERIOT_TOOLS env var to default profile Open

CHERIoT-Platform/devcontainer#62 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Clean up MTDC Open

CHERIoT-Platform/cheriot-sail#21 · 20 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
CSRs that can be accessed without `PERMIT_ACCESS_SYSTEM_REGISTERS` should be specific to compartments Open

CHERIoT-Platform/cheriot-sail#22 · 13 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Extending support for DII execution mode Open

CHERIoT-Platform/cheriot-sail#24 · 5 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Specify background zeroizer Open

CHERIoT-Platform/cheriot-sail#31 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Specify background revoker Open

CHERIoT-Platform/cheriot-sail#32 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
MCAUSE/MTVAL for illegal SCR addresses Open

CHERIoT-Platform/cheriot-sail#34 · 2 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Libraries accessing Read/Write data through caps stored within PCC Open

CHERIoT-Platform/cheriot-sail#39 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
CSub redundant? Open

maybe-v2

CHERIoT-Platform/cheriot-sail#40 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
v2? isentry support Open

maybe-v2

CHERIoT-Platform/cheriot-sail#41 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
v2? cgp as SCR Open

maybe-v2

CHERIoT-Platform/cheriot-sail#43 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Optimise bounds encoding Open

CHERIoT-Platform/cheriot-sail#45 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
v2? Permuted capability encoding optimized for 33-bit busses Open

maybe-v2

CHERIoT-Platform/cheriot-sail#46 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
misa reports incorrect value in Sail Open

CHERIoT-Platform/cheriot-sail#55 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Incorrect behaviour when registers greater than 15 used as destination in certain instructions Open

CHERIoT-Platform/cheriot-sail#67 · 1 comment · 1 reaction · 0 assignees · Indexed Sep 14, 2026
Revised encoding with fewer degenerate cases? Open

maybe-v2

CHERIoT-Platform/cheriot-sail#69 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Rethinking the bounds calculations Open

CHERIoT-Platform/cheriot-sail#75 · 15 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Tweak cincaddr so that it can replace cmove instruction Open

maybe-v2

CHERIoT-Platform/cheriot-sail#88 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
v2? revisit RV C encodings? Open

maybe-v2

CHERIoT-Platform/cheriot-sail#89 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Clear tag on store capability violation? Open

CHERIoT-Platform/cheriot-sail#91 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Should user mode counter CSRs be accessible / exist? Open

CHERIoT-Platform/cheriot-sail#95 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
CRAM/CRRL should depend on base and length Open

CHERIoT-Platform/cheriot-sail#96 · 14 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Root-stability of permissionless forms? Open

maybe-v2

CHERIoT-Platform/cheriot-sail#98 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
RISCV-CHERI wants to always seal in `jal{r,}`; is that OK? Open

CHERIoT-Platform/cheriot-sail#100 · 1 comment · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Caps returned back to the caller cannot be not protected Open

CHERIoT-Platform/cheriot-sail#102 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
MTCC/mtvec(c) is not initialized as per TestRIG's desires Open

CHERIoT-Platform/cheriot-sail#115 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Initialization confusion Open

CHERIoT-Platform/cheriot-sail#116 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
MEPCC/mepc is not initialized as per TestRIG's desires. Open

CHERIoT-Platform/cheriot-sail#118 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
Missing rs data in RVFI Open

CHERIoT-Platform/cheriot-sail#119 · 4 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026
[maybe v2] (Compressed) auipcc.base? Open

enhancement maybe-v2 question

CHERIoT-Platform/cheriot-sail#128 · 0 comments · 0 reactions · 0 assignees · Indexed Sep 14, 2026

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